| Communications Physical Layer (PHY) Development Development of Standards Based Physical Layer Modulators and Demodulators in FPGA or ASIC Modulation Formats: OFDM QAM QPSK 8-VSB GSM Capabilities: Viterbi Decoding, Reed Solomon Decoding, Variable Rate Filtering, Carrier Recovery, Symbol Timing Recovery, Channel Estimation, Equalizetion, Synchronization Standards: IEEE 802.16 (WIMAX) DVB-S, DVB-C ATSC, DVB-H GSM/GPRS, GPS, WIMEDIA ATSC System Analysis, Simulation and Algorithm Development: SPW and Matlab Implementation: Altera Quartus, Verilog |
| Michael Paff Mr Paff has extensive experience in developing baseband hardware for satellite communication, cable modems, cellular and fixed wireless systems. He is capable in system design, modulator/demodulator implementation and forward error correction implementation. He holds patents in the areas of cable modem and satellite receiver and OFDM technology. He has participated in cable modem standards process and IEEE 802.16a standards activity. He has a BSEE from Bucknell Univerity and an MSEE from Syracuse University. Mr Paff is a strong believer in FPGA verification of complex communication algorithms. He is fully equipped to develop and test FPGA prototypes using Altera technology. Mr Paff can augment your design team by providing existing logic IP cores for modules such as Viterbi Decoder, Reed Solomon, OFDM modulator/demodulator or variable rate RRC filter, He can implement a custom module to your specifications. He can provide system engineering support or help troubleshoot immediate problems. |
| Recent Projects Pineapple Technology (2007) Develop Altera core for ATSC transmitter to be compatible with DVB-ASI and SMPTE 310 serial input interfaces. Loral Space Systems (3/06 - 12/06, 7/07- present) Simulation of calibration algorithms for complex phased array spacecraft hardware. Commstack/Focus Enhancements (3/04-3/05) Develop ASIC FEC Logic (Verilog) for 802.15 3a UWB modem Commstack/ Focus Enhancements (11/04- 12/05) Develop ASIC Logic (Verilog) for 880 Mega bit-per-second Viterbi decoder RFID Tag (3/04-3/05) Developed tag-to-reader protocol for unique, low cost RFID system Hyundai/Hynix (2000) Developed variable rate demodulator conforming to DVB-S to be used in tuner product to be sold in Asia. Also developed DVB-C prototype. |
Paff Engineering
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| mpaff@paffengineering.com 650 941 2954 or 650 704 9645 (cell) Los Altos CA 94024 |
Satellite
Cable Modem
UWB
WIMAX
FEC
Point-to-Point
Cable Modem
UWB
WIMAX
FEC
Point-to-Point
Algorithnm Development
Modeling & Simulation
Logic Implementation
Prototype Development
Modeling & Simulation
Logic Implementation
Prototype Development